AMD, Intel and TSMC agree on a single chip interconnect standard

Leading technology companies, including AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung and TSMC, announced the formation of a consortium for the joint development and implementation of an open standard for chiplet interconnection - Universal Chiplet Interconnect Express (UCIe). The result of this work was the first version of the UCIe 1.0 specification.

The purpose of the standard is to simplify the possibility of creating multi-chiplet chips using semiconductor chips from different vendors. The UCIe 1.0 specification standardizes on physical and logical levels the inter-chip interconnects, and defines aspects of implementation, such as the electrical protocol, software model, compatibility testing procedures, etc., among other things. The UCIe 1.0 protocol is based on the PCI Express and Compute Express Link industry standards.

In this way, leading semiconductor designers and manufacturers have come together to form a unified ecosystem for the creation of complex chips, which are expected to be multi-chip designs in most of the future. Following the UCIe 1.0 specification will allow the free design of combined solutions, composed of chips from different developers, produced in different semiconductor factories with different processes.

The UCIe 1.0 specification takes into account the existence of different chiplet packages - both standard 2D and more advanced 2.5D (using interconnecting chip-bridges). Obviously, in the future the specification will expand to full 3D-chiplets.

The use of widespread PCIe and CXL protocols at the logical level allows developers to get flexible and compatible connections with high bandwidth and low latency, which according to performance parameters will be suitable for work with memory and I/O-blocks as well. The UCIe specification also includes off-chip device connectivity to enable electrical and optical connections to external components.

The UCIe 1.0 specification defines the inter-chip data transfer rate (from 4 to 32 billion transactions per second), latency (less than 2 ns), bus width (from 16 to 64 bits, depending on the package), contact density (pin spacing from 25 to 130 µm) and connection conductor length (up to 25 mm). Naturally, the 2.5D-chiplets in this case have higher performance figures, but require shorter conductors. In general, for 2D-chiplets the connection bandwidth limit is limited to 125 GB/s per mm2, while for 2.5D-chiplets can have connections with bandwidth up to 1350 GB/s per mm2 of the chip area.

It is worth recalling that Intel has previously offered an open standard for chiplet interconnect - Advanced Interconnect Bus (AIB) - it is still used in conjunction with EMIB technology. But it is not compatible with UCIe 1.0. Instead, the consortium decided to use the more mainstream PCIe and CXL variants, so Intel will change its implementation of interchip connectivity later - the company has confirmed that it is willing to do so.

The UCIe consortium is also open to other companies not currently in it. Thus, Nvidia, which is not among the founders of UCIe, can join the consortium later.


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